In this thesis, Asymmetric and Symmetric High Voltage PMOS devices based on 90nm BCD(Bipolar-CMOS-DMOS) technology had been studied.BCD technology incorporates analog components on a single die.by integrating three distinct typed of components on a single die, this technology helps to reduce the number of components. Fewer chip components further reduce the area required on the board, this driving down costs. The integration also helps to reduce the parasitic losses than would typically be seen in a non-integrated solution. Power management is a important and highly growing market in semiconductor industry. The future growth of power management is mainly driven by mobile phones, computer market, infrastructure replacement, alternate energy market and improving efficiency of existing electronics. POWER MOSFETs with the inherent advantages of fast switching response, excellent thermal stability and high input impedance have recently begun to displace power bipolar transistors in high-frequency switching applications. One important concern related to power MOSFETs is the reduction of the specific on-resistance. Symmetric and Asymmetric HVPMOS for 90nm BCD technology has been developed and optimized to obtain better electrical performance and to meet the specifications provided by industry. This aging phenomenon that threatens the circuit and product lifetime warranty is it to be considered as the key challenge in reliability. HCI has been one of the critical reliability tests. The Hot Carrier Injection test for high voltage PMOS has been studied. For the PMOS, threshold voltage(Vth) degradation and drain current saturation(Idsat) degradation due to hot carrier injection stress has also been observed for both Symmetric and Asymmetric HVPMOS.
郭伯臣 KUO,BOR-CHEN;時文中 SHIH,WEN-CHUNG
In recent years one of the most interesting trend is the emergence of specialized process technologies, especially the Bipolar-CMOS-DMOS (BCD) process technology, which is typically used to make products where high power or voltage ideally needs to be controlled by a digital controller BCD technology incorporates analog components (Bipolar), digital components (CMOS) and high-voltage transistors (DMOS) on the same die. In this work we have developed a high voltage NMOS with the asymmetry and symmetry structures to integrate with the advanced 90nm BCD process. In the BCD process the main constrain is the process conditions, because process conditions are not optimizable for each device. So, we have developed device optimizing technique with the fixed process conditions by using the synopses TCAD simulation tools. We have successfully developed a 20V asymmetric and symmetric NMOS and from this optimization technique and we can go up to 40V with the fixed process conditions. We have developed both asymmetric and symmetric device and symmetry device has the advantage of interchangeable source and drain, this is very suitable to design layout with interchangeable terminals. Hot Carrier Injection (HCI) is a phenomenon in solid-state electronic devices where an electron or a hole gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. In this study we have examine how device design parameters can affect degradation due to the hot carrier injection in high voltage NMOS devices with symmetry and asymmetry layouts. We have simulated the Hot Carrier Injection by using the thermodynamic simulation models. According to reliability models, a short-channel MOS transistor is susceptible to the device characteristics degradation due to the hot carrier injection (HCI) effect. In this study, we describe an anomalous degradation behaviour that is opposite to the general understandings on the high-voltage NMOS transistor. We explored causes to this unusual degradation and device optimization techniques to improve the HCI degradation.
陳永欽 CHEN, YEONG-CHIN;陳兆南 CHEN, CHAO-NAN
When devices are designed in a demanding market like automotive industry, safety devices, sensors, led drivers, switching power supply, etc accurate and consistent assessment methods to evaluate quickly the quality, reliability, robustness and “safe operating area” or SOA of new products are required. In this thesis, reliability, robustness and “safe operating area” or SOA for ultra–high voltage devices based on 0.6um BCD process has been investigated and performance has been improved by using unique device structure and process design engineering without use of any additional mask. Failure mechanism of ultra high voltage junction field effect transistor (UHV-JFET) under unclamped inductive switching (UIS) test is investigated. UHV-JFET device with an unclamped inductive load would force the device in reaching the avalanche breakdown during ON- to –OFF state transient. We explain the ruggedness failure of the Power MOSFETs based on drain impact ionization event, diffusion current through the impact ionization area further enhancing the impact ionization level. Sentarus sdevice simulation has been used for UIS test. It is well known fact that variation in dose affects the diffusion current in turn varying the stability of the device. An optimum drain engineering technique based on device structure, drain implantation method and doping profile gradient indicates that the avalanche current and avalanche energy capability per micron device width can be enhanced up to 26.6% and 67.6% respectively. In power management integrated circuit application and BCD integration, the lateral double-diffuse MOS (flat LDMOS) transistor, Source Centric (SC) and Drain Centric (DC) with higher breakdown voltage has long been integrated in IC process. These devices are often used as output driver, and directly connected to pin. Without additional electrostatic discharge (ESD) protection devices, the power device have to discharge the ESD stress themselves. Because of the ultra-high operating voltage, the power dissipation of these devices is extremely high, thus this device is susceptible to burn out. In order to get better ESD robustness, we propose an ESD self-protected Source Centric (SC) and Drain Centric (DC) devices structure with SCR, poly capacitor and a thin oxide in the drain-poly gap region. This structure can improve the self-protection capability of the SC and DC devices for ESD, because this structure can distribute the current from drain to poly capacitor, so that the transistor effect occur earlier.
Design of a 90nm BCD Integrated High Voltage NMOS and HCI Degradation Dependence on Device Design Parameters
許健 GENE SHEU
由於基於金融科技區塊鏈技術下的各種線上虛擬貨幣的盛行–例如數位貨幣比特幣，新的網路犯罪也利用各種相關平台已取得不法財物，例如勒索軟體。因此，在本篇論文中，我們使用彩色Petri網（Coloured Petri Net）分析客戶端面對勒索病毒威脅之行為模式，並進一步提出模擬勒索病毒進行之狀態改變與客戶端若具備資訊安全素養時的兩個面向的案例探討。本文的貢獻如下：利用彩色Petri網（CPN）分析與描述客戶端面對勒索病毒威脅時的情境，從而給出適當的以及足夠的資訊安全素養教育訓練能得到更強健的個人防衛能力。最後，可藉由著色標記（color token）的轉移情形來分析並掌控勒索病毒的下一步威脅的目標，提供客戶端面對勒索病毒時處理該威脅之方法。
MUNTHA SAI DHEERAJ
Design and Optimization of HVPMOS Devices and Hot Carrier Reliability Test with 90nm BCD Technology
本研究主要目的在建立一個成績資料庫，並透過雲端平台的服務，讓親師利用行動載具來了解學生的學習狀況，並探討家庭背景是否影響學習的表現，期望開發出來的資訊系統，可以做為教學的診斷，提早發覺學習的瓶頸，讓親師協助學生克服問題，順利邁向另一個學習目標。本研究利用visual studio 2010及SQL資料庫系統，利用關聯性資料表的特性，建置一個電腦技能測驗資訊系統，可以迅速查詢學生的學習表現及與家庭環境的交叉影響，得到的結論就電腦技能而言，父母親的婚姻狀況健全、經濟狀況愈佳及學生性別為女生，學生的學業成就愈高；而父母親的教育學歷高低及母親是否為外配，與學生的學業成就並沒有明顯的關連性。本研究透過雲端平台服務及系統彙整的結論，讓親師可以即時掌握學生的學習情況，提供適切的關懷及補救教學，讓學生充滿信心參與在學習的行列中。關鍵字：SQL、家庭背景 、電腦技能